Reliability Evaluation of One-Pass and Two-Pass Techniques of Assembly for Package on Packages under Torsion Loads

Package on Packages (PoP) find use in applications that require high performance with increased memory density. One of the greatest benefits of PoP technology is the elimination of the expensive and challenging task of routing high-speed memory lines from under the processor chip out to memory chip in separate packages. Instead, the memory sits on top of the processor and the connections are automatically made during assembly. For this reason PoP technology has gained wide acceptance in cell phones and other mobile applications. PoP technology can be assembled using one-pass and two-pass assembly processes. In the one-pass technique the processor is first mounted to the board, the memory is mounted to the processor and the finished board is then run through the reflow oven in a single pass. The two-pass technique has an intermediate step in which the memory is first mounted onto the processor. Then, these two parts are placed in a carrier tray and reflowed. These joined devices are then mounted on the circuit board and the finished board is reflowed a second time. The two-pass technique has a distinct advantage in that the PoPs can be checked for defects before final assembly using a non-destructive test (such as X-Ray) and hence one would expect higher yield. For this study, identical test vehicles were assembled with eight PoP packages assembled with SAC105 and SAC125 solder for the bottom BGA and top BGA respectively. One-pass technique and two-pass technique were used to assemble two test vehicles each. These test vehicles were evaluated under mechanical torsion loading to establish if method of assembly used has any impact on the mechanical fatigue durability. This was followed by failure analysis to determine failure sites. Time to failure data was plotted as Weibull 2-parameter distributions and ANOVA analysis was performed. No statistically significant difference was found in the reliability of the packages assembled using the two different techniques. KEYWORD: Assembly techniques, Package on packages, Lead-free solders, Torsion loading, Reliability assessment, E-SEM, ANOVA, Dye and Pry technique. INTRODUCTION: Package on package (PoP) technology involves vertical stacking of two or more packages to allow better density. PoP configurations conventionally involve stacked memory chips or integrated memory and logic chips. Memory chips conventionally require fewer IOs when compared to logic chips. For this reason standard configurations involve a low pitch (high density) package with processor on the bottom package and the higher pitch (low density) package with the memory chips (stacked or otherwise) on the top package. Ball grid array (BGA) packages are conventionally used in PoP applications due to their high IO density and reliability [1, Error! Reference source not found.]. A schematic of a conventional package on package is shown in Error! Reference source not found.. Figure 1: Package on package technology Some of the obvious advantages of package on package technology are more efficient utilization of board space, easier routing and lower transmission time between processor and memory chips, better electrical performance with lower noise [1]. And this can be achieved using only “known good” packages since the memory and logic packages can be tested separately As originally published in the IPC APEX EXPO Conference Proceedings.